Memory provides data storage for electronic systems. Flash memory is one of various memory types, which has numerous uses in modern computers and devices. A typical flash memory may comprise a memory array that includes a large number of non-volatile memory cells arranged in row and column fashion. The cells may usually be grouped into blocks. Each of the cells within a block may be electrically programmed by charging a floating gate. The charge may be removed from the floating gate by a block erase operation. Data may be stored in a cell as charge in the floating gate. NAND memory array may comprise a basic architecture of flash memory.
In recent years, vertical memory, such as three-dimensional (3D) memory has been developed. A 3D flash memory (e.g., 3D NAND memory array) device may include a plurality of strings of charge storage devices (memory cells) stacked over one another, with each charge storage device corresponding to one of multiple tiers of the device. The charge storage devices of a respective string may share a common channel region, such as one formed in a respective pillar of semiconductor material (e.g., polysilicon) about which the string of charge storage devices may be formed.
In another dimension, each group of the plurality of strings may comprise, for example, a group of strings sharing a plurality of access lines, known as wordlines (WLs). Each of the plurality of access lines may couple (e.g., electrically or otherwise operably connect) the charge storage devices (memory cells) corresponding to a respective tier of the plurality of tiers of each string. The charge storage devices coupled by the same access line (and thus corresponding to the same tier) may be logically grouped into memory pages, when each charge storage device comprises a multi-level cell capable of storing two bits of information.
In a third dimension, each group of the plurality of strings may comprise a group of strings coupled by a corresponding data lines, known as bitlines (BLs). A 3D memory may be divided into memory blocks, comprising a plurality of memory pages, selectable via drain-side select gate (hereinafter select gate drain (SGD)) devices and source-side select gate (select gate source (SGS)) devices that may be provided over each end of the pillars to control memory cells. A 3D NAND memory array may utilize floating body pillars with SGS and SGD at the edge.
A read operation of the 3D NAND memory array may comprise access of data stored at a particular memory location of the memory array. Prior to a write (program) operation to a specific block of the memory array, the specific block may first be erased with the application of high voltages.
A program operation may require the careful application of high voltages to a selected memory location, followed by a program verify operation to ensure that the data has been properly programmed. Furthermore, since high voltages are used, the flash chip may be designed to be relatively tolerant to inadvertent programming of non-selected (e.g., deselected) memory cells. Generally, a memory cell may be programmed by applying a high voltage to its gate while keeping its source and drain terminals grounded.
The high electrical field may cause electrons in the memory cell channel to cross the gate oxide and embed in the floating gate (known as Fowler-Nordheim (F-N) tunneling), thereby increasing the effective threshold voltage of the memory cell. Programming may be typically done by the page or block, meaning that all the memory cells in the block connected to the same wordline may be selected to be programmed with write data (e.g., logic “0”) at the same time. The remaining memory cells may be unselected (deselected) during programming. Since the memory cells start in the erased state (logic “1”) prior to programming, only the memory cells to be programmed with the logic “0” may be subjected to the high electric fields necessary to promote F-N tunneling.
During program operation, at least one memory block of a memory array may be selected for programming, while other blocks of the memory array may be deselected. In the selected block, due to the physical connections of the memory array, all the memory cells along the same wordline may receive the same high voltage programming level. As a result, erased memory cells may have their threshold voltages unintentionally shifted. A program inhibit scheme may be used for preventing those memory cells where no change from the erased state is required, from being programmed to the logic “0” state. More specifically, the program inhibit scheme may be used to increase a pillar potential so that unintended programming of the memory cells that are not supposed to be programmed does not occur. The pillar potential may increase through boosting a current channel of program-inhibited pillar.
However, pillar potential increase may cause a leakage current in the boosted current channel of a program-inhibited pillar. To prevent it, current common source (SRC) of the memory array may be biased to a finite positive voltage to make the pillar's gate to source voltage negative, to reduce the leakage from the boosted channel of the program-inhibited pillar. On the other hand, biasing SRC may increase the leakage current of pillars of deselected memory blocks, which in turn may increase the operation current of the memory array.